Discrete cosine transform (DCT) is a widely used tool in image and video compression applications. Adders and multipliers are the main components in the DCT implementation. Recently, the high-throughput DCT designs have been adopted to fit the requirements of real-time applications. This paper proposes a pseudo carry compensation truncation (PCT) scheme for errorcompensation using multiplexer which deal with the truncation errors and to achieve low-error and highthroughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. The design is implemented using VHDL on 0.18μm technology and proposed truncation scheme is applied to an image compression algorithm.