This study shows a turbo decoder utilize the multiple soft-in-soft-out decoders (SISO), that decodes one code word.This decoded will allow simultaneous execution over the multiple successive trellis stages. Issues related with approaches are collision problem, critical path delay and operating efficiency. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. By using the contention- free-Interleaver and Dynamic Voltage Frequency Scale (DVFS) algorithm, the performance of the decoder will be improved with low power.